От: fpga journal update [news@fpgajournal.com]
Отправлено: 10 марта 2004 г. 2:04
Кому: Michael Dolinsky
Тема: FPGA Journal Update Vol II No 10


a techfocus media publication :: March 9, 2004 :: volume II, no. 10


FROM THE EDITOR

This week we are inundated with innovation. Our first feature article looks at three recent product launches that broaden the reach of FPGA technology into new domains. AccelChip’s DSP solution, Altium’s Nexar, and Xilinx’s new serial backplane programmable line card solutions would appear on the surface to have nothing in common, but all three exemplify the trend in focusing on a target market with finely-tuned solutions.

Our second feature article looks at a fascinating CPLD announcement from Altera this week. While MAX II may sound like just another CPLD, under the hood, a surprise awaits those who follow the architectural trends in programmable logic. Max II certainly raises the stakes in CPLD and it will be exciting to watch the results.

Our contributed article this week comes from Dan Ganousis at AccelChip and looks at top-down methodologies for DSP design targeting hardware implementation. New FPGAs offer compelling capabilities for DSP designers, but the devil is in the design flow. Dan explains a methodology that smoothes out the bumps in the DSP-to-FPGA road.

Thanks for reading!

If there's anything we can do to make our publications more useful to you, please let us know at: comments@fpgajournal.com

Kevin Morris – Editor
FPGA and Programmable Logic Journal


LATEST NEWS

Tuesday, March 9, 2004

Opal-RT Unveils RT-LAB TestDrive

Leading EDA Vendors Get on Board With MAX II Devices

Xilinx Simplifies High-Speed DDR-I Memory Interfacing With New Turn-Key Design Kit

Xilinx Expands Distribution Channel to India Through Nu Horizons Electronics Corp.

Xilinx Announces Release of Free ISE WebPACK 6.2i Delivering Up to 50% Faster Spartan-3 Design Performance

Insight Memec Ships Xilinx Spartan-3 LC Development Kit; Learn the Fundamentals in Our Hands-on Workshop Beginning March 16, 2004

Express Logic's ThreadX RTOS Support Expands to Include Both the Xilinx MicroBlaze Soft Processor Core and Virtex-II Pro Embedded Powerpc Processor Core

Mentor Graphics Expands Higher Education Program in China to Help Cultivate IC Design Growth

QuickLogic and System General Announce Next-Generation

General Micro Systems Announces Industry's Smallest Single-Board Computer Device Programmer

Monday, March 8, 2004

Altera Takes Radical New Direction with MAX II CPLDs

Opal-RT Technologies Launches New Family of FPGA I/O Products

Opal-RT Technologies Introduces SignalWire

Cavium Networks Introduces Industry's First SPI Bridge Processor Family for Enterprise and Service Provider Equipment

Xilinx to Demonstrate Latest CPLD Solutions at Wireless Systems Design Conference & Expo 2004

Altera's New MAX II CPLD Family Delivers Dramatic Reduction in Cost and Power Consumption

Xilinx Announces Acquisition of Triscend Corp.

Xilinx Introduces Second-Generation CPLD Design Kit

Xilinx Reports Broad Adoption of Virtex-II Pro IBM PowerPC Solution

Xilinx Virtex II-Pro Performance Wins Confidence of Barco for Air Traffic Control Component

WELLS-CTI Adds BGA Socket Line; Tsunami Covers Demand; Solidifies Supplier's Grid Array Offering

New Cadence Allegro Platform Delivers On-Target, On-Time, High-Speed System Interconnect Design

Xilinx Reports Strong Revenue Growth in CPLD Business

Wednesday, March 3, 2004

Anadigm Receives Control Engineering 2003 Engineer's Choice Award for AnadigmPID


ANNOUNCEMENTS

Learn a Bunch, Save a Bundle with Insight Memec/Xilinx FPGA Workshops

Xilinx Spartan™-3 Workshop -- Design with Spartan-3 FPGAs and ISE design tools. Get the Spartan-3 LC development kit for under $200 (USD).

Xilinx Virtex-II Pro™ UltraController™ Workshop -- Design with Virtex-II Pro FPGAs and UltraController solution. Get the Virtex-II Pro LC development kit for under $200 (USD).

*Attend a workshop free when you order a Spartan-3 or Virtex-II Pro LC development kit from Insight Memec.

Spartan-3 Workshop
http://www.insight.na.memec.com/s3_workshop
Or call 800.677.7716

UltraController Workshop
http://www.insight.na.memec.com/uc_workshop
Or call 800.677.7716

Visit Techfocus Media

CURRENT FEATURE ARTICLES

Aftermarket Avalanche
New Products Propel FPGAs into a Broader Base
A Wolf in Sheep's Clothing
Altera introduces MAX II
Top-Down DSP Design Flow to Silicon Implementation
by Dan Ganousis, AccelChip, Inc.
Physics Drives Physical into the Mainstream
New demands on design tools
Accelerating VoIP
A. Tavoularis, M.G. Manousos, D. Economou,
G. Lykakis (National Technical University of Athens)

All is Not SRAM
A survey of flash, antifuse, and EE programmable logic
DSP on FPGA Reduces System Cost
BeHere Technologies Harnesses Stratix with ImpulseC
Peter Baran, Be Here Technologies
Ralph Bodenner, Impulse Accelerated Technologies
Joe Hanson, Altera
Emulation on the Cheap
ASIC prototyping with FPGAs
Aurora Lightweight Gigabit Serial Protocol
by Abhijit Athavale, Xilinx, Inc.
Mr. Moore's Wild Ride
90nm FPGAs go mainstream


Aftermarket Avalanche
New Products Propel FPGAs into a Broader Base

One indicator of a maturing market is the introduction of products at the peripheries. New add-ons to the core capability are introduced that make the main item more valuable and useful to a wider variety of customers. Recently, a wave of new products has hit the market that promises to bring programmable logic to new audiences. These are not new devices or bigger, better, faster FPGA design tools. They are one step removed. They bring specific capabilities to specific markets that bridge the gap, allowing new projects to take advantage of programmable logic technology in a new way.

Let’s look at three newly introduced technologies and how they bring new applications into the programmable logic domain. We’ll check out AccelChip’s offering that brings FPGA-based hardware acceleration within reach of DSP designers, Altium’s Nexar which allows board-based system designers to harness the power of SoC FPGAs, and Xilinx’s line of line-card solutions that promise to do for the backplane-based communications industry what FPGAs did for the, well, backplane-based communications industry, actually. [more]

A Wolf in Sheep's Clothing
Altera introduces MAX II

In 1967 Andy Granatelli showed up at the Indianapolis 500 with a different kind of race car. Instead of the usual shriek of a high-performance racing engine, the car flew past the grandstands with a quiet “whoosh”. It was faster than the other entries at the race that year – much faster. The turbine-engine car had a tremendous advantage over its reciprocating-engine rivals. Parnelli Jones drove the car in the lead for 171 laps before a simple bearing failure took it out of the competition.

The question immediately arose: Is this really a race car? By jumping to a design that was more akin to a jet engine than a traditional racing powerplant, Granatelli had challenged the status quo by attacking the common notion of the underlying engineering architecture.

Just over a decade later, in 1988, Dennis Conner showed up at the America’s Cup challenge with a different kind of America’s Cup yacht. Instead of the usual graceful monohull design with billowing sails, Conner’s boat was a high-tech catamaran design, comprised of two parallel streamlined hulls powered by a vertical wing-like airfoil. His Stars and Stripes catamaran beat challenger New Zealand by two of the widest margins ever recorded in the event.

The question arose before the race ever began: Is this really an America’s Cup yacht? In responding to an unexpected challenge, Conner had also challenged the status quo by attacking the common notion of the design.

About 16 years later, (this week, in fact) Altera announced MAX II, a new super-low- cost, low-power CPLD. Instead of the usual PAL-like macrocells arrayed on the CPLD architecture, MAX II has something no one expected: look-up tables (LUTs). This is a different kind of CPLD with higher density, lower dynamic power, and higher performance than existing CPLD families. [more]

Top-Down DSP Design Flow to Silicon Implementation
As DSP design teams transition to hardware implementation of DSP algorithms for higher performance, a new DSP design methodology is required to automate the flow from algorithms to silicon.

by Dan Ganousis, AccelChip, Inc.

We’re on the threshold of the next wave of rapid growth in high technology. During the 1970s, we witnessed the proliferation of semiconductors that enabled the digital generation. In the 1980s came the decade of dynamic memories (DRAMs) as semiconductor vendors perfected their manufacturing technologies to allow dramatic increases in memory capacity at previously unheard of prices. The 1990s will be remembered as the era of microprocessors as even the casual consumer became extremely literate about Megahertz and motherboards. And now, as we’ve entered the new millennium, digital signal processing (DSP) has become the technology of focus with consensus expectations of exponential growth. “Everybody knows that DSP is the technology driver for the semiconductor industry,” says Will Strauss, an analyst with Forward Concepts Co., Tempe, AZ. [more]


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